The present disclosure relates to built-in self-test (BIST) devices and methods, and more specifically, to structures and methods that reduce the time for testing memory arrays connected to a common BIST controller.
Silicon chips are being populated with increasing amounts of memory and logic as technologies progress. Power demand due to simultaneous use of these memories can cause disturbances to the power supply. These voltage disturbances can cause memories or logic to fail due to operation outside of the rated voltage range.
As more memories are integrated onto chips and the power density of those chips increases (increasing watts per square mm) the risk that simultaneous access of memories will cause logic or memory failures increases greatly. Typical chip function will operate a subset of memory content at any one point in time in order to manage power consumption. Power supply decoupling capacitance can be added to chip and board designs to mitigate transient voltage disturbances and larger power supplies and/or improved cooling mechanisms can be applied to support higher power usage in general, but all of these solutions are expensive in terms of chip area and system cost.
Memory BIST (built-in self-test) is an important tool for testing memories (including finding/diagnosing and repairing defects within those memories). As more memory is integrated into chips thorough BIST test and repair is a requirement in order to ensure reasonable product quality/reliability levels. To improve BIST quality oftentimes more test patterns are run as part of manufacturing test. Total test time can take many millions of cycles when all necessary test patterns are included.
Memory BIST is designed to operate as many memories as possible simultaneously, while still avoiding false failures due to over test (due to exceeding the power specification for a certain chip design). For a given chip design, this might be a small subset, whereas for other chip designs this could include virtually all memories. In addition, memory BIST should be able to test with some margin compared to the normal functional application in order to produce good SPQL (shipped product quality level) while minimizing impacts to yield.
High quality memory test and repair via extremely thorough test needs to be balanced against test time. Test time can be a major cost component of chips (sometimes reaching into the multi-minute range). Anything that can be done to reduce test time is valuable.
In an ASIC chip design system an automated methodology for inserting memory BIST and generating manufacturing test patterns is needed in order to produce an economical method for providing test infrastructure. However, most automated methods that use a single BIST engine to test multiple memory instances simply program the BIST to test the largest possible memory. This is the easiest method for performing the test. When the BIST enters an out of bounds region of the address space test logic specific to each memory (specific to each memory's address space size) will convert the BIST operations to write operations to non-existent addresses (when aliasing is not possible) or to read operations (where the results are simply ignored). This “out of bounds” detection logic is common practice.
Some test insertion methods use either hardware based or software based programming to attempt to shrink the address space/reduce test time. For hardware-based programming, an inventory of all memories attached to a BIST must be taken and the maximum address of the BIST adjusted. This is done prior to logic synthesis. For software-based programming, an inventory of all memories attached to a BIST must be taken and the maximum address of the BIST adjusted (programmed via override logic that can take a large amount of chip area). Either method is complicated and difficult to implement and verify. The consequence of not adjusting the maximum address space of the BIST correctly would be un-tested regions of memories (which could be disastrous from a quality standpoint).
Consequently, a robust (low risk) mechanism for adjusting the BIST address space dynamically using existing test structures (with minimal additional area overhead) would be highly desired to reduce test time/cost.